Research And Design Of Motion Estimation Hardware Architecture For VLSI

Multimedia communication has been most popular in the life of human beenings'.With the development of internet, Multimedia communication has been the most important part .With the improvement of technology, there is an ongoing global trend to shift multimedia applications from traditional platforms, such as PC and set-top box, to PDA PPC and smart phone. Because of the limit of processor, there is a challenge of video codec for real-time. International video coding standards facilitate the wide use of video coding, and the open key algorithms in video coding standard determine the performance of the video coding. As the most computationally demanding and important part of video coding, motion estimation is the important research part of video coding.This thesis aims at the researching on FPGA of Low I/O bandwidth and high throughput motion hardware implementation of estimation algorithm. In this paper, we firstly introduce technology of video coding and its history, and discuss the principle and technical indexes of block matching motion estimation. Then we introduce classic Full-Search motion estimation arithmetic and fast search arithmetics, such as Three-step search arithmetic, Diamond search arithmetic and two-dimension search arithmetic. With analyzing these algorithms, we discuss the situation of the local-result of fast search arithmetic. Then we introduce the classic hardware architecture of motion estimation arithmetic, such as 1-D systolic array, 2-D systolic array and tree architecture for the hardware resources,processing rate,I/O ports. With using data-interlacing method, a new Data Flow and corresponding two-dimensional systolic array is proposed, it can efficiently reuse data to decrease I/O bandwidth with high throughput. This architecture is developed from a parallel VLSI architecture for FS. And they are designed, implemented and simulated with Verilog HDL, Quartus II and Modelsim. At last, the whole motion estimation module for new architecture is tested. According to the simulation waves and experiments data, we can draw some conclusions as follows: first, the motion estimation module designed in this thesis can implement FS algorithm correctly and can export the right result. Secondly, the architecture designed for FS is proved to be advanced and real-time realizable through the research on the use of hardware recourses and clock frequency.