Researches On Key Algorithms In Video Coding Based On VLSI Implementation

Multimedia communication especially the video communication has been one of the most interesting research topics since 1990's because of its wide application. With the improvement of technology, there is an ongoing global trend to shift multimedia applications from traditional platforms, such as desktop PCs and set-top boxes, to hand-hold devices (e.g. PDAs and smart-phones), which results in some new constraints (e.g. power efficient and cost efficient) for VLSI implementation of video codec. International video coding standards greatly facilitate the wide use of video coding, and the open key algorithms in video coding standards determine the performance of the video coding. Motion estimation and rate control algorithms are exactly the open key algorithms in current international video coding standards. This dissertation investigates the motion estimation and rate control algorithms in international video coding standards based on VLSI implementation with some achievements. Some results have been integrated into a commercial video codec chip.The main contributions and innovation points of the thesis are as follows:1. A fast low-complexity motion estimation algorithm called layered quasi-full search which can be easily realized by VLSI is proposed based on the VLSI architecture of 1-D systolic arrays for full search block matching. The computational complexity of the proposed algorithm is a quarter of that of full search, while the performance of it is comparable to that of full search. The proposed algorithm is not only robust but also has the advantages of simple computational flow and regular data flow which are beneficial for VLSI implementation. The VLSI architecture of the proposed algorithm is also presented in this thesis with the result of hardware realization.2. A fast low-complexity half-pixel motion estimation algorithm is proposed as well as the mathematical models which can reflect the relation between the integer pixel motion estimation and the sub-pixel motion estimation. In the proposed algorithm, the half-pixel accuracy motion vector is obtained by a fair polling among the three half-pixel accuracy motion vectors which are computed directly from the results of integer motion estimation according to the three different mathematical models. This algorithm is free of half-pixel interpolation and block matching, so it can be implemented by VLSI cost efficiently. The experimental results show that the proposed method can obtain good-quality reconstructed images.3. An efficient programmable motion estimation processor is proposed with its VLSI...