Design And Implementation Of Motion Estimation Circuit For Mobile Computing

With the continuous development of network technology and integrated circuit industry,real-time video processing for mobile applications becomes more and more popular.And the video resolution extends from SD to HD.Mobile products released in recent years have begun to support the playing and recording of videos under latest coding standard HEVC,which indicates that the HEVC standard will gradually spread in mobile devices.Video encoding is a computationally intensive process that consumes a large amount of computational resources and at the same time generates enormous power consumption.The duration of supporting for high-definition video applications has been the weak point of mobile devices.With the more complex coding process of HEVC,the battery life of mobile devices will face greater challenges.Therefore,how to realize low complexity and low power real-time encoding for HEVC videos on mobile devices is an important research direction.Using low complexity algorithm and corresponding low power VLSI design for the motion estimation module,which accounts for 50% of the total encoding computation process of HEVC,is studied in this paper.After researching the encoding quality and computational complexity of three kinds of motion estimation algorithms,including predictive hexagon-based fast search algorithm,the low bit representation algorithm and gray-code representation algorithm,the predictive hexagon search algorithm is selected according to the PSNR loss.In the low-power design of the circuit level,the lowest 2 bits of the 8-bit pixel are abandoned to reduce the power consumption.The PSNR loss of the video image is 0.39% compared to the whole 8-bit algorithm,and it is acceptable.In the design process of the VLSI architecture,the data flow characteristics of selected algorithm supporting variable-sized block motion estimation in HEVC are analyzed.Combined with the data multiplexing characteristic of the hexagon search template,broadcasting reference pixel array is used in the PE array structure,which effectively reduces the on-chip memory access times.Using SMIC 65 nm technology to implement this circuit,the maximum operating frequency is 250 MHz,and the number of gates used is 110 K.The power consumption is 58.38 mW.It can meet the real-time encoding requirement of HD video(1920 × 1080,30 frames per second).