| H.264, is the newest video coding standard of ITU-T VCEG and ISO/IEC MPEG .This new standard is designed for the application in the areas such as broadcast, interactive or serial storage on optical and magnetic devices such as DVDs, video-on-demand or multimedia streaming, and multimedia messaging etc. over ISDN, DSL, Ethernet, LAN, wireless and mobile networks. Some new features of the standard that enable enhanced coding efficiency by accurately predicting the values of the content of a picture to be encoded are variable blocksize, quarter-sample-accuracy and multiple reference picture for motion estimation and compensation. The new features increase the complexity and computation load of motion estimation greatly in H.264 encoder. Motion estimation is usually carried out in two steps– integer pel and fractional pel motion estimation, among which the former one takes most of the computation load of the whole process. Experimental results have shown that motion estimation can consume over 50% of the total encoding time of H.264 codec. Due to this reason, in order to get real time performance from an H.264 encoder parallel processing must be exploited in the architecture.Based on studying VLSI architectures of fixed block size motion estimation for H.264, the paper proposes one integer and one fractional motion estimation VLSI architectures to get high data reuse. The main work is as following:1,Motion estimation algorithem for H.264 reference software is researched. Firstly, the procedurce of H.264 motion estimation and mode decision is introduced. Then the procedure of macroblock coding is introduced. Finally, standard sequences were tested with different tools and reference software.2,Fixed size motion estimation VLSI architectures are researched. Firstly, the data reuse of motin estimation is analyzed and importance of high data reuse VLSI architectures is emphasized. Then both C level and D level data reuse VLSI architectures are introduced. Finally, fixed size motion estimation VLSI architectures are compared and extended with various sizes.3,One new high data reuse VLSI architecture for H.264 integer pixel motion estimation is proposed, which is suitable for high memory bandwidth of high resolution video coding. Based on one fixed size motion estimation VLSI architecture, variable size computing is implemented with crosss network. This VLSI architecture has D level data reuse through using on-chip RAM. The experiment result shows that it can realize real-time motion estimation for SHDTV (1920x1080)@60Hz video with search range [-8, 7], it consists of 208K gates and 30.7K RAM, operates at 123.49MHz. The chip area is 4mm×4mm.4,One low cost and high data reuse VLSI architecture for H.264 motion estimation is proposed, which is suitable for portable multimedia devices. This VLSI architecture employs 4x4 PE (processing element) array to compute serially 16 SADs (sums of absolute difference ) of 4x4 block sizes in one 16x16 block,then use one SAD merging module to get SADs of larger block size. The search area data and current block data can be highly reused in the 4x4 PE array. This architecture has been designed and synthesized in HJTC 0.l8um technology. The result shows it consists of 79K gates and 0.9KByte SRAM, operates at 48.6MHz. The architecture allows the real-time processing of CIF at 30fps in a search range [-8, +7]. The proposed VLSI architecture greatly reduces the memory bandwidth and hardware cost which are very suited for portable devices.5,One new VLSI architecture for H.264 fractional motion estimation which adopts 1/2 and 1/4 parallel search is proposed. This architecture implements all fractional pixels interpolation and uses 49 4-parallel PEs. This architecture has been designed and synthesized in HJTC 0.l8um technology. It consists of 276k gates when operating at 147MHz. It can meet SDTV(1280x720)@30Hz video coding motion estimation requirements. Compared with other architectures, this architecture has high throughput and low memory access requirement. |
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