The Research Of NCL Circuit Computing Targeted At Block Cipher Processing

Asynchronous integrated circuit generates the local signals instead of global clocks, so it resolves such problems as clock skew and energy dissipation in traditional synchronous integrated circuits. The design of cipher algorithms chip based on asynchronous integrated circuit is the new research direction of the cipher chip. This paper has analyzed the characteristics of NCL circuits and the operation characteristics of block cipher algorithms, and reached the processing technology of block cipher algorithm based on the NCL circuit.This paper has analyzed the operation and processing structure characteristics of popular block cipher algorithms, and then concluded the circuit type, the processing structure and the design technique of the asynchronous block cipher chip. Based on the NCL circuit, this paper has proposed the circuit model targets at block cipher processing. The model adopts the parallel non-linear closed pipelines structure and linear and non-linear mixed handshake mode. This paper has mapped AES and IDEA on the model both in the forms of closed pipelines and opened pipelines.This paper has reached the designing method of dual-rail cipher module. By the two steps of synthesis, this method realizes the NCL circuits based Muller C element and OR gate. Based on that, this paper has designed dual-rail cipher function module in AES and IDEA, and analyzed deadlock in NCL circuits and proposed the solving mechanism.This paper has validated NCL circuits on gate level, unit level and cipher level respectively. In synthesis, the design is fabricated on 0.18um CMOS cells and Balsa 1μm cells to guarantee the accuracy of the circuit model on its function and timing. The paper has also validated the NCL circuit deadlock solving mechanism and analyzed the performance of closed pipeline and opened pipeline.To sum up, this paper has analyzed the design technique of asynchronous block cipher chip, designed the block cipher processing model based on the NCL circuits and mapped AES and IDEA algorithms on the model. This paper has also designed the dual-rail cipher function module. Aimed at deadlock in NCL circuits, this paper has brought forward a mechanism to solve it.