Design And Analysis Techniques Of Asynchronous Embedded Microprocessors

The past five decades have been dominated by synchronous processors with global clocks. Recently, however, heightened interest in low power consumption and clock skew has encouraged the use of asynchronous techniques as a viable approach to future circuits design. This thesis details our developments in the asynchronous integrated circuits design methodology, performance modeling and analysis of asynchronous pipelined circuits, architecture and microarchitecture development issues of embedded microprocessor. Primary innovative works in this paper can be summarized as follows:(1) We developed an asynchronous integrated circuits design methodology based on macro cell design. The design methodology uses many existing synchronous EDA tools. The critical circuit components of the control path of asynchronous circuits are designed as macro cell. The data path of the asynchronous circuits is designed with traditional synchronous design methodology. We developed an asynchronous 32-bit multiplier to verify the design methodology. The design also verified the advantages of asynchronous circuits in performance and power consumption.(2) We proposed several methods for performance modeling and evaluation of the asynchronous circuits based on queueing network theories. Queueing network modelling is a particular approach to computer system modeling in which the computer system is represented as a network of queues which is evaluated analytically. The asynchronous pipeline rings are modeled with closed queueing network with blocking, and the asynchronous pipelines are modeled with open queueing network with blocking. Both of the models were analyzed with approximate algorithms to obtain the performance parameters.(3) We proposed several methods for performance modeling and performance evaluation of the asynchronous circuits based on Petri net theories, and methods to optimize the performance of timed circuits. We developed an approach to derive the average cycle period of timed circuits. Two different analysis methods were proposed. One is based on analysis of P-invariants, which is suitable for high level abstraction of asynchronous circuits; the other is based on integer linear programming method, which is suitable for circuit level abstraction of asynchronous circuits. We proposed asynchronous circuits retiming algorithm based on cycle period analysis approach. This optimization problem is solved by mixed integer linear programming program.(4) We designed the architecture of a 32-bit embedded microprocessor, and implemented a synchronous version of this architecture. The architecture definition were used as a specification for both synchronous and asynchronous microprocessor design. The design of the instruction set, exception model and memory hierarchies etc. were discussed. The issues about microarchitecture design, logical and physical implementation of the chip were discussed in detail. The design of on-chip bus and other peripheral equipments were introduced in brief. The chip was implemented in 0.18μm process. The operating frequency is 266MHz. The research on synchronous microprocessor forms a basis for our asynchronous microprocessor research.(5) We designed a prototype of asynchronous microprocessor based on our architecture specification. Our design methodology based on the combination of macro cell design and de-synchronization techniques were used. At the end of the thesis, the preliminary results of performance evaluation were given. The prototype of asynchronous microprocessor verified that our design methodology, methods for performance modeling and evaluation, techniques for architecture and microarchitecture design of microprocessor are effective and can be used in asynchronous microprocessor design.