Research On The Design And Implementation Techniques Of Asynchronous Data Triggered Architecture

Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. Effciency and flexibility are crucial features of processors in the embedded systems. The embedded processors need to be efficient in order to achieve real-time requirements with low power consumption for specific algorithms. And the flexibility allows design modifications in order to respond to different applications. The architecture and design methodology of embedded microprocessor encountered great challenges. Under the current integrated circuit manufacturing process, it is significant to study the new architecture and design methodology of the embedded microprocessor.In this thesis, the Asynchronous Data Triggered Architecture is presented, which is a new embedded microprocessor architecture. The design methology of Application Specific Instruction-set Processor (ASIP) and asynchronous circuits to embedded microprocessor are adopted, in order to achieve the best trade-off among real time performance, power consumption and design flexibility. We put many efforts on the design and implementation techniques of this new architecture, including the hardware/software automatic co-design environment, the design methodology of asynchronous circuits, the design of asynchronous function units and the reconfigurable segmented interconnect network. Based on these research works, we have developed microprocessor two low-power embedded microprocessor prototypes.Primary innovative work of this thesis can be summarized as follows:1. Asynchronous Data Triggered Architecture (ADTA) was proposed. The ADTA is a new architecture of embedded microprocessor. This architecture can be scaled and customized for different applications. This architecture can support complex function units and register files. This architecture can provide both flexibility and configurability, while new function units, register files can be added without any restrictions. The hardware/software automatic co-design environment provides best support to the effective design, implementations and simulation of the ADTA microprocessor. The microprocessor is globally synchronous and locally asynchronous implementation using not only synchronous function units but also asynchronous function units. This architecture has low power consumption without performance loss, and it is very suitable for the embedded systems that are sensitive to power dissipation and performance.2. A design methodology of asynchronous circuits was proposed. This design methodology was based on macro cell and uses the existing synchronous EDA tools as many as possible. The critical circuit components of control path of the asynchronous circuits were implemented by customized macro cell. And the datapath circuits were implemented using the traditional synchronous design methodology.3. The critical asynchronous function units of the ADTA were proposed and implemented. The efficiency of the proposed design methodology of asynchronous circuits has been proved. It is very important for research and implementation to solve relevant problems of asynchronous circuits design. The evaluation of the performance and power consumption shows that the asynchronous function units have lower power consumption without performance loss.4. The reconfigurable segmented interconnect network of ADTA were proposed. The driver and receiver of the low-swing circuits were implemented, and the driver and receiver circuits were customized as macro cell. The method for delay and power consumption modeling and the evaluation of the low-swing circuits is presented, that can be used to evaluate and optimize of the interconnect network during the design. We also investigated segmented interconnect bus and algorithm for routing and optimization. The segmented bus architecture can reduce the delay and power consumption of the interconnect network. By using low-swing circuits and segmented bus, the reconfigurable segmented interconnect network obtains low power and delay.5. Based on research works of ADTA, two low-power embedded microprocessor prototypes for two different applications were implemented. Two microprocessor prototypes were implemented under 0.18μm process. By executing the application program, both microprocessors have lower power consumption than their synchronous version.The successful implementation of two microprocessor prototypes verified the research works of critical techniques of ADTA. It showed that the ADTA has low power dissipation without performance loss and was suitable for design of embedded microprocessor.