Gate level pipelining optimization, energy estimation, and design for test techniques for asynchronous null convention circuits using industry-standard design tools

This dissertation focuses on developing algorithms for design automation of NULL Convention Logic (NCL) circuits using industry standard CAD tools. Automated design flows will enable rapid development of high-performance, energy-efficient, and testable NCL circuits, which will expedite the integration of widespread asynchronous circuit usage in the semiconductor industry, thus alleviating many of today's clock and power related problems. The dissertation is organized into three papers, as described below.; The first paper discusses an automated throughput optimization algorithm based on Gate Level Pipeling techniques. The method produces an optimally pipelined NCL system with significantly increased throughput over the original non-pipelined design. It is applicable to dual-rail and quad-rail designs using the full-word completion strategy.; The second paper discusses an approach for fast and efficient energy estimation for delay-insensitive (DI) systems, based on gate-level switching. The approach has been automated, and utilizes a VHDL-based simulation to perform the estimation. The paper also describes an approach for simulating a transistor-level design controlled using a VHDL testbench, which is critical for asynchronous circuits, since the inputs change based on handshaking signals, instead of periodically in response to a global clock.; The third paper discusses two different DFT implementations aimed at making asynchronous NCL designs testable, by enhancing the controllability of feedback nets and observability for fault sites that are flagged unobservable. The work also includes a novel methodology to solve the critical issue of testing stuck-at-faults on the internal feedback paths of NCL threshold gates.