Research On Key Techniques On Design Of Data-driven Asynchronous Microprocessors

With shrinking of the sizes of semiconductor technologies, more and moretransistors can be integrated in a single chip. At the same time, the problems of largeclock skew, high power consumption and low reliability are becoming more and moreserious. Recently, heightened interest in low power consumption and elimination ofclock skew has encouraged the use of asynchronous techniques as an alternativeapproach to circuit design. However, the lack of CAD tools for asynchronous circuitdesign is still a big challenge for the development of asynchronous microprocessors.This thesis details our researches on some key techniques of data-drivenasynchronous microprocessor design, which includes automatic critical path analysis,deadlock checking, high-level simulation and performance estimation in data-drivenasynchronous circuits. A coarse-grained data-driven asynchronous design flow whichconcludes all the techniques mentioned above is proposed. The correctness andeffectiveness of the design flow is evaluated by implementing a data-drivenasynchronous microprocessor used in security area. The main contributions of thisthesis are listed as follows.(I) We develop an automated methodology for the critical path analysis indata-driven asynchronous circuits. By leveraging the modularity of asynchronouscircuits, we solve the critical path analysis problem at two levels seperately: thecomponent level and the gate level. Combinational loops in asynchronous circuits areautomatically broken by using a width-first search method. We propose a multi-sourcelongest-path algorithm to calculate the delays between latches. The critical paths areselected on a constraint basis. The delay distributions in data-driven asynchronouscircuits can be analyzed in a polynomial time complexity. In order to improve thethroughput, a critical path based latch insertion strategy is implemented in a data-drivenasynchronous circuit design tool named Teak. Experimental results on two large designshave shown the effectiveness of our methodology.(II) We propose a structure-based deadlock checking method in data-drivenasynchronous circuits. Much previous work on deadlock checking in asynchronouscircuits relies on a reachability analysis of the circuits’ states. Instead, we proposed analternative approach focusing on the structural properties of well-formed asynchronouscircuits that will never suffer deadlocks. The sufficient and necessary conditions for acomponent network consisting of Steer, Merge, Fork and Join are given. The slackelasticity of the channels is analyzed in order to introduce pipelining. As an application,a deadlock checking method is implemented in Teak. The proposed method shows agreat runtime advantage when compared against previous Petri net based verificationtools. (III) We propose a simulating method which is based on an Event-Behavior modelto do the simulation and estimation of data-driven asynchronous circuits. Traditionalsimulation-based throughput analysis methods cannot achieve both accurate in estimatesand quick in runtimes. To our best knowledge, by now there are no simulating toolsspecially designed for asynchronous circuits. Designers often use synchronous designtools to do the simulations of asynchronous circuits at a later stage of the design period,which may cost a long runtime. Based on an Event-Behavior model, we implemented anevent-driven simulator named Esim at the component level. Delay information ofcomponents is automatically added while building the model. Execution traces duringthe simulations are recorded for throughput optimization. Experimental results onseveral designs show both the accuracy of the throughput estimation method and theefficiency of the throughput optimization techniques.(IV) We propose a coarse-grained data-driven asynchronous design flow whichconcludes the critical path analysis method, the structure-based deadlock checkingmethod and the event-driven simulation method mentioned above. Based on a set ofdata-driven components, pipelined asynchronous circuits can be efficiently constructed.We optimize the circuits by combining components to form coarse-grained pipelines.Different from the Macro Cell based method which needs the insertion of delayelements, the asynchronous circuits design using the coarse-grained design flow is quasidelay-insensitive. The robustness of asynchronous circuits is preserved by thecoarse-grained data-driven asynchronous design flow.In order to validate the correctness and efficiency of the coarse-grained data-drivenasynchronous design flow, we implemented an asynchronous microprocessor designedfor security named NanoSpa. Experimental results show the coarse-grained data-drivenasynchronous design flow can be used to design and implement high power-efficientasynchronous microprocessors.