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Research And Design Of The System Of Video Transmission In The Wideband Intergrated Digital Optical Synchronous Network

Posted on:2010-07-12Degree:MasterType:Thesis
Country:ChinaCandidate:N XueFull Text:PDF
GTID:2178360278975790Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Wideband Intergrated Digital Optical Synchronous Network (WIDOSNet) is a new concept in industry control network, it can transmit the information of voice and video not only efficiently, but also flexibly. It is based on the conception of the next generation network (NGN), to change the traditional centerx to divergent selection. In this network, all users can transmit the data to the concentrator with the default rate, then the concentrator will collect and handle the data from the users. At last, it will send the data to all users. The users will select the data they need from those data. The concentrator just plays the role of data transmission at variable speed. Ostensibly, it changes the user's independent signal path into the public channel of the redundant information, but it will solve many problems about complicated exchange because of the high performance of FPGA and selecting the fiber-optical as the media for transmitting. Thus, this method will reduce the complexity of the switch design. So, WIDOSNet will have wide prospects of market.Firstly, this paper mainly introduced the basic principle, the structure, the technical features and functions of WIDOSNet, and expounded its frame structure and transmission modes. And then, the paper compared WIDOSNet with the industrial Ethernet, to point out the advantages of WIDOSNet.Secondly, the paper designed and finished the system of video transmission by the NCU Node Control Unit of WIDOSNet. The first step is using the I2C bus module of FPGA to make the reasonable configurations for the chip ADV7181B with its output the PAL video data which is in accordance with the standards of CCIR656, 27MHz clock frequency, the 8 bits wide of 4:2:2YCrCb. The second step is using Verilog HDL language to decode, interpolate, de-interlace,compress and so on. After handling, under the control of the NIOSII soft core, the video data is cached into the SDRAM by the way of ping pong operation. The data is then read to the NCU Node Control Unit from the port of the NCU Node Control Unit. The third step is using JMF programming platform to design the interface of video for operation, to make the video transmission of WIDOSNet more intuitionistic and easy to operate. Finally, the paper pointed out the shortcomings of the design and the problem which need to be improved in the future.
Keywords/Search Tags:WIDOSNet, video transmission, FPGA, Verilog HDL
PDF Full Text Request
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