The Design Of Video Acquisition System Based On FPGA

With the development of society, constantly enrich the material wealth of society,out of consideration a variety of factors, society demands for real-time videosurveillance system is becoming increasingly intense, performance requirements aresteadily growing. Electronic technology, video processing technology rapiddevelopment both in hardware and software, enabling us to be the growing needs oftoday’s reality, but also to provide new solutions for video surveillance design. Videosurveillance systems can be divided from the functions of video data collectionterminal, data transmission and monitoring client side. Video capture directly affect thedesign of the front end of the video signal for speed or efficiency requirements underthe level of the video surveillance system to meet the requirements of the data neededto design a high speed, the tip having to upgrade a large video processing space.The design involves a more popular video capture program, the application ofprogrammable logic device for video data collection, use SOPC technology andcollaboration in the design of hardware for video signal completed acquisition:Building Nios II soft-core processor on the FPGA collaborate video memory chips tocomplete the data collection; Useing Verilog HDL hardware description language andresources on FPGA to complete the video signal acquisition. Based on Verilog HDLlanguage’s parallel processing features,Nios II soft-core will hand over control of thesystem to achieve global regulation eventually. Video Capture System data willconverted data collected from CMOS sensor to640X480RGB format, To be able tovisually display video data, video signals displayed on the320X480LCD screen inthis design and make it easy for debugging. Specific design features are as follows:Designed with Altera’s FPGA which is popular in desin as the video front-end processor, which instead of the traditional PC as the core controller. Theminiaturization of acquisition front reduce costs, power consumption, and facilitate thetransmission of video data for next; Based on SOPC technology which build Nios IIsoft-core processor on FPGA software completed video data acquisition; By VerilogHDL hardware description language to complete the video signal acquisition; Nios IIsoft-core video capture permissions after completion of initialization to FPGA,self-regulation of the steering system. Therefore, the Nios II control system has morelogic resources to complete extensions or docking with the next level of the system.This design use Quartus II9.1to completes the hardware logic circuits andcustom IP core in Verilog HDL language to describe the choice of developmentenvironment; Using IP cores in SOPC Builder and standard components to build NiosII soft-core greatly simplify the design difficulty; Using Nios II9.1IDE completed theC firmware development and the system eventually captured video display validationresults achieved in the TFT-LCD.Through the design shows the relative to the traditional AISC which hassignificant flexibility and meet the requirements of the present stage of video data,provides an efficient way for the subsequent development of video surveillancesystems.