Design And FPGA Implementation Of Improved RS Codec Algorithm In Digital TV Systems

With the increasing vigor of the BeiJing Olympics, Digital TV industry in china has been developed by leaps and bounds. This issue was just from the project QAM modulator, which accords with the national digital television standard DVB-C.Reed-Solomon (RS) code is one class of the important linear block codes in the error control area. For having the ability to correct gusty errors and random errors synchronously, especially the burst errors, RS code has been widely used in a variety of error control programs. QAM modulator adopts the RS (204, 188) code for its coding mechanism in National Digital TV DVB-C Standard.Combining with a new Constant Coefficients GF(2 m) Galois Field Multiplier, in this paper, An improved RS encoder algorithm ,which has a feature of high-speed and low-complexity, was designed and implemented by FPGA. By downloading the algorithm programs to the Xilinx's Spartan-3E family devices in hardware testing, the functionality has been verified and a waveform has been given in the paper. To facilitate the following QAM demodulator related work, this paper has also designed a RS decoder implemented on FPGA.Main work in this paper follows.1. We introduced the mathematical basis of RS coding, and completed the mathematical deriving process for RS coding theory.2. A conventional design method for the core components ~ Galois Field Multiplier, was given in the paper.3. We proposed a new type of Galois field multiplier, and designed an improved algorithm RS encoder. The design has simplified the hardware circuit and reduced the system costs. The correctness of the design has been verified through the implementation on FPGA。4. A RS decoder was designed and implemented on FPGA, which has passed through the functional simulation, and RTL circuit has been obtained.