Research On Technology Of Reconfigurable Galois Field Arithmetic Unit Targeted At Symmetric Cipher

Galois Field Arithmetic is the critical nonlinear blocks of symmetric cryptography. There are two methods for implementing the arithmetic operations. One is to use general processor, the other is to use hardware directly.The former has sufficient flexibility and extendability, but it has the low executive performance, couldn't meet the requirement of high speed communiacation. Adversely, the latter can operate at a high speed, but its adaptability is relatively poor, so that it couldn't meet various needs of cryptographies. Aiming at above contradiction, this thesis adopted reconfigurable technology to design the hardware structure of Galois Field arithmetic unit, The structures could not only support different arithmetic operations of symmetric cryptographies, but also meet the requirement of high performance.Based on the analysis of symmetric cryptographies, combining the characteristics of basic arithmetic operate in Galois Field with the feature of arithmetic unit structure in ciphers, this paper systematically summarized the identities of arithmetic operation unit, and analyzed the reconfigurable element of arithmetic unit in Galois Field.Based on the research on the theories and circuits of Galois Field multiplier, this paper presented the reconfigurable architecture for Matrix Multiplier, which could flexibly support different Matrix Multipliers based on various multiplicative operate and dissimilarity dimension. Based on the theory of Isomorphic Field, a reconfigurable structure targeted atσ-LFSR feedback functions was proposed in this paper, which can accomplish the feedback functions ofσ-LFSR with different width state element and operation in different types of Galois Field.By analyzing different algorithms and hardware structures of Galois Field inverse operation deep, combining with the conclusion of optimized polynomial, this thesis proposed an optimized model for Galois Field inverse and mapped the model to fields with different extension degrees. The reconfigurable structure can achieve the tradeoff between delay and area of circuit, which can realize inverse of Galois Field with different field polynomial flexibility.As to the reconfigurable structures above, the designs were implemented on FPGA to simulation function of the hardware structures, and were synthesized on 0.18um CMOS cells through Design Compiler tool to compare with other hardware/software implementation. The results indicate that the reconfigurable structures of Galois Field operate units in this paper can implement both flexibly and effectively.