Design And Implementation Of A 2.5Gbps Clock Data Recovery Circuit For PCI Express

With the default of high power consumption and low speed, the conventional parallel bus is to be replaced by the high-speed serial bus, such as PCI Express. Clock and Data Recovery (CDR) circuit is the key part of the PCI Express. The critical task of CDR is the recovery of the clock embedded in the non-return-to zero (NRZ) serial-data stream. The recovered clock both removes the jitter and distortion in the data and retimes it for further processing.The research objective of this thesis is to analyze, design, and implement high-speed clock and data recovery circuits for 2.5Gbps that can be readily implemented in an integrated, low-cost, low power CMOS technology.In this paper, the system model of CDR is established, and the estimation method of the CDR loop parameters and device parameters been researched, and then the design flow of high speed CDR circuits is advanced; moreover, the design method of circuits and layout of high speed digital and analog mixed circuit are researched; finally, the test chip for CDR is designed and the test method of high speed analog circuit is analyzed.In the design process a novel differential voltage-controlled oscillator, with high frequency, low jitter and better control voltage range, is designed. To overcome the disadvantage of traditional charge pump circuit, an improved charge pump circuit which has a very high bandwidth and a better solution on the charge current overshoot is proposed; meanwhile, an initial circuit was proposed, which not only enforces the reliability of CDR, but also saved the time that CDR required for locked. Finally, designed and implemented a 2.5Gbps CDR by full-custom design method fabricated in 130nm digital CMOS technology without the aide of external references. It's area is 175um*240um. According to the simulation result of post-layout, it's proved that the CDR can conform to PCI Express specification, for the CDR can recovery any input data patterns correctly, the power consumption is 32mW and the root mean square jitter less than 0.01UI which is 4ps.