Research And Design Of ESD Protection Of Integrate Circuits In Deep Sub-Micron CMOS

A perfect designing of Electrostatic Discharge (ESD) protection circuit is very important for integrate circuit in reliability. The research in this article mainly aims at the ESD protection circuit, which is the key technology of the reliability of IC system in sub-micron meter process. On the base of research result and progress in several years, the thesis design two sorts of practical ESD protection circuits, one in 0.25μm CMOS in X processor and the other in 0.18μm CMOS in Y processor, and in which it is optimized from circuit structure level to layout level. The circuit is succeeded in two chips. The test results of the ESD circuit are well coincident with GJB548A-96 standard. It is well for the relative I-V characteristic, while the pulse of pin keeps on 8KV.This thesis mainly contributes to the following aspects.1. It studies the ESD principle , failure mode, ESD model and the characteristic of ESD elements. It also points out the effect of snap-back MOS in ESD protection circuit.2. This paper designs a couple of ESD protection circuit for I/O Buffer. It analyses some factors which constrain the ESD protection circuit structure, snap-back, latch-up and charged-device model of input buffer. Based on improvements on these factors, the whole performance of input buffer is greatly improved. It is improved for the driving structure, double guard ring and poorly driving of output buffer and the circuit capability is better. Noise and ESD, which has great influence on VDD/GND buffers, is also paid attention to in this paper. There is little influence for the simulation results of the I/O Buffer circuit using ESD protection circuit.3. Based on improvements on the factor of ESD protection circuit in whole chip, the performance of IC is greatly improved. To avoid the unwonted damage of internal circuit with sorts of VDD/GND, this paper optimizes the circuit structure. Noise, which has great influence on whole chip ESD protection circuit, is also paid attention to in this paper.4. With the 0.25μm CMOS technology ( ESD implanting ) and the 0.18μm CMOS technology ( ESD implanting ), this paper designs a ESD protection circuit of whole chip structure on designed circuits and structure of power separately. Layout is also improved by the research of new progress.5. It studies the theories of circuit test. It puts forward some methods of testing ESD protection circuit. It also points out the way of reading testing result.