| Recently video devices, personal computers and broadband access technology are fast developing. At the same time,3D processing, video exchanging and complicated computation work lead to quick expanding of the data. In order to satisfy the constantly increasing requirement of big volume data exchanging work among processor, memory, peripheral devices and network devices, more and more high speed interfaces, such as DDR, USB, SATA and XAUI are introduced. Nowadays speed unit for these high speed interfaces is Gbps and the popular DDR3 interface has a speed of 1.6Gbps, SATA2 can reach 3Gbps. The new interface such as SATA3.0 has a speed of 6Gbps.The traditional method used to test high interface needs to implement high performance tester which has the same or higher speed as DUT in order to do function test and parameter test of the interface. Adapting this test methodology requires advanced capability of Automatic Test Tester (ATE), thus push up the test cost. The popular ATEs which can satisfy Gbps speed testing requirement are Teradyne Flex, UltraFlex and Verigy Pinscale93000RF. But cost of these ATE is pretty high, which can reach 150 USD/h. For a complicated SoC chip, only the high speed interface needs very high test speed while the other parts can be tested at low speed. These complicated test code will also occupy a lot of the tester time, add more test cost and low the competitiveness of product. Thus, it is a worthwhile task for tester engineers and designers that testing chip with high speed interface without using high speed ATE.Thesis chooses a chip with 3Gpbs XAUI interface as a study target. With the help of specific DTF(Design for Test) circuit, finally complete mass production test program which achieves the function and DC parameter of the high speed interface on low speed and low cost ATE. Studying of this thesis verified that this test mythology is economical and efficient method for high speed interface testing. |
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