Design And Implementation Of Asynchronous Function Units For Transport Triggered Microprocessors

As the embedded applications are growing more complex and diversified, it puts forward higher requirements with the performance, power consumption, cost and other targets of embedded microprocessors. The architecture and design methodology of embedded microprocessors which have widely used hence faces with great challenges. And embedded microprocessor designers have to discover new architecture and new circuit design methodology to meet the increasing demands of different applications well.In this thesis, we combined transport triggered architecture with asynchronous circuit technology for embedded multimedia applications. We presented a transport triggered microprocessor architecture oriented to multimedia application, and then used asynchronous circuit technology to design and implement the key function units. According to these research works, we proposed a prototype structure of transport triggered microprocessor based on asynchronous function units.(1) First of all, based on its characteristics, we configured the parameters of the transport triggered microprocessor architecture oriented to multimedia application. And transport triggered architecture has the advantages of modularity, simple structure, flexible design and so on. We get the meaningful parameters by analyzing the multimedia applications. These parameters provide guidance to design transport triggered microprocessor. Based on the results of analysis, this thesis presented the framework of transport triggered microprocessor architecture, whose proportion of functional units and configurations are all in line with the specific demands of multimedia applications.(2) Second, we designed and implemented an asynchronous 32-bit sub-word parallel Multiply-Accumulate Unit (MAC) by the asynchronous integrated circuits design methodology based on macro cell in 0.18μm process. The data path of this unit uses a special partial product generator, which takes the accumulator as part of the partial product to reduce the delay. And the unit's power consumption are superior to the synchronous counterpart due to the asynchronous circuit design.(3) At the same time, we designed an asynchronous sub-word parallel ALU unit, which can complete the arithmetic, shift, logic, expansion of multimedia computing and so on. The adder is the core of the ALU, and its performance greatly influence to the performance of the entire ALU, so we laid a strong emphasis on the design of sub-word parallel adder. The ALU was implemented in 0.18μm process and the results of the evaluation show that the performance of asynchronous ALU is close to synchronous ALU which has the same data path, but the power dissipation of asynchronous ALU is much lower. (4) Finally, we proposed a prototype structure of transport triggered microprocessor based on asynchronous function units. According to the architecture of transport triggered microprocessor oriented to multimedia applications and the asynchronous function unit encapsulate model, we proposed a prototype structure of transport triggered microprocessor based on asynchronous function units by adopting asynchronous MAC and ALU. This structure mixed the advantages of transport triggered architecture together with asynchronous circuits, so it offers an excellent design template for high-performance, low-power embedded applications. We provided a preliminary evaluation of the structure to study the influence which asynchronous function units affects to transport triggered microprocessor.