Design And Implementation Of Functional Units For Low-power Data Triggered Microprocessor

With the rapid development of the semiconductor technology, the problem of power consumption has become a challenge for the designers of microprocessors. This problem is more serious in embedded domain. In one aspect, the performance of the embedded microprocessors is increasing rapidly with the boom of application requirements. This makes the power consumption become higher. In the other aspect, battery is the main power source in most embedded systems, so the energy is limited. The study on low-power techniques is of great sense in embedded domain.This thesis introduces the low-power design methods in functional units of data triggered architecture microprocessor. The fixed-point functional units are optimized through dynamical operands detection technology. The floating-point functional units are optimized through asynchronous circuits design technology. According to these research works, a low-power asynchronous data triggered microprocessor is implemented. The primary works in this thesis are listed below.1. We do lots of research work on data triggered architecture. Data triggered architecture has the advantages of modularity, simple structure and so on. We configure the parameters of the data triggered microprocessor core according to the analyze results of multimedia application. Based on the characteristic of the application and the architecture, we choose dynamical operands detection and asynchronous circuit as the technologies to reduce the power consumption in the microprocessor.2. We design and implement a low-power fix-point multiplier through dynamical operands detection. The value bits of each operand are divided into three groups and the invalid groups are identified through zero-detection module. After receiving the control signals from the detection module, the following modules can avoid the computing process if it is not necessary. Experimental results show this optimizing method can reduce the multiplier's power consumption.3. We design and implement a low-power floating-point multiplier and a floating-point adder using asynchronous circuit design method. The data paths of the asynchronous units are pipelined and the control paths are designed according to the redundant four-phase latch control protocol. Experimental results show these two technologies do reduce the floating-point units'power consumption.4. We design and implement a low-power data triggered microprocessor in UMC-0.18μm CMOS technology. The processor has a synchronous DTA core and an asynchronous DTA core. Experimental results show the asynchronous core's power consumption is 43%~65% of the synchronous core's power consumption.