Research And Design Of The Data Nodes Subsystem Of Wideband Intergrated Digital Optical Synchronous Network

The phase in of the next generation network and the requirement of the new business greatly increased the use ratio of the network. As the cost of optional access network and the technique, it becomes to the principal restriction of the network multi-business amalgamation, restricts the broadband development of the whole communication network. As the "last kilometer" of the information super highway, technical study of the access net becomes to the focal point currently.The appearance of the broadband generated data synchronous optical network can just fulfill this demand, it technically base on Synchronous Digital Hierarchy(SDH), Optical Fiber Communication, SOPC technique etc, with multiprocessor structure by high speed programmable chip, make the system have adequate information processing power; by fire new conception of dynamic situation data flow regulation, to adjust the transfer speed of the network any time as requirement, thereby the network resource can be used more efficiently. The network structure is in the form of network structure, integrated service device (ISD) uses the concept of data selection on the plate to complete traditional function of exchange. 125μs cycle time slot is adopted for the generated data Synchronous Optical of the broadband to process data transfer, suitable for transmission of speech signal as some real-time control command, also make it convenient for the Backbone Network, such as Synchronous Digital Hierarchy(SDH).The thesis processed research mainly on data node of broadband generated data synchronous optical network. as the constituent of the node integrated server, data node is responsible for all kinds the data access except speech sound and video frequency. On the basis of the analysis of the other existing access model, protocol and characteristics, the thesis discuss detailedly the design and implementation of the hardware and software of the data nodes subsystem. First, from the overall completed the theoretical research and design of content of the data nodes subsystem; then, built a hardware platform with second generation Cyclone series FPGA of EP2C8Q208 of Atera Corporation as the processing center. Brief introduction has been make on the development process of the hardware platform, including the each data interface module circuit of the system, the node bus interface circuit,and FPGA configure circuit and circuit of the SDRAM memory, with the technology of development of embedded system built a NIOS II soft-core processor as the system control center in the platform; the design of software code and relevant driver, the Nios II application program code are also designed after completion of the hardware platform, the transplantation ofμC/OS-II in Nios II is completed at last.