Design Of DDR2 Controller With The Cache Of Reducing Writing Delay Of DRAM Based On FPGA

With the rapid development of Internet technology and increasing demand of network performance, on the one hand, network application requires more and more on performance of security gateway devices, on the other hand, the application of security gateway products is more and more wide, firewall from the typical extended to UTM, IPS and so on. These applications have powerful capabilities of message analysis and traffic analysis, also need to forward the flow efficiently which passes by the equipment. From the common view of security gateway products, although they have different scenes, they all required CPU has a strong ability to ensure analytical work and work forward. The limitation of ability of CPU makes forward job occupy the resouse which analytical work needs. Product application development staffs have to spend a lot of energy on balance of performance and functionality. Network performance has become a problem which affects the improvement of function, Under such circumstance Network Security Accelerator emerged.The DDR2 controller with the Cache of reducing writing delay of DRAM based on FPGA is designed for NSA. The main role of DDR2 controller is to control read and write of network packet, and its embedded Cache is mainly used to eliminate delay time of DRAM of DDR2 controller and accelerate system speed. Because this project is implemented with FPGA, in this paper, the internal CAM of FPGA is used to achieve Cache in order to reach the purpose of reducing writing latency of DRAM. Compared with the traditional Cache, it is simple and easy to realize, saving resource within FPGA, and the performance is not worse than the traditional Cache. It accelerates the speed of the returned date and improves the system performance.The concept, function, structure and principle of the initial Cache are introduced first in the paper, and the design programme and process of the DDR2 controller and the embedded Cache are then elaborated. Its simulation and Authentication have proved that the programme is scheduled to realize the requirements of the project to solve the exsiting problems.