Design And Implementation Of Image Scaling System Based On FPGA And DDR2

As a basic operation of digital image processing, Image Zoom hs been widely used in the field of Remote sensing, monitoring and medical care.It is very important to research on image scaling. The traditional image zooming is implemented on PC, due to the restriction of the structure of CPU, the computing speed is not high, can not satisfy the real-time applications requiring high bandwidth. In view of this situation, this paper designed the image scaling system based on FPGAand DDR2.This paper first introduces the principles and realization method of nearest interpolation, bilinear interpolation and cubicinterpolation And then discusses in detail the design of image scaling system platform. The detailed design including PC, MCU and FPGAcircuit board.Then describe the use of SPARTAN-6 MCB.Finally, realize the nearest neighbor interpolation algorithm, and achieved good experimental results.The core of system platform design is the design of FPGAcircuit board.The main FPGAchip is Spartan-6 LX-75.the MCU is C8051F021.The bord’s characteristic is that it use High speed memory device DDR2 as the cache chip.It uses the MCB controller inside the SPARTAN-6 chip to control the write and read operation of DDR2. On the board,author complete the logic design of nearest neighbor interpolation algorithm.The characteristic of logic design is that it uses the multiplier IP inside the chip,and it complete the nearest neighbor interpolation algorithm on the basis of the cache of DDR2.Compared with the traditional way based on the Interpolation by convolution,it is more close to the results of the original image scaling algorithm. And,this method simplified the control of the data flow.Lastly,the paper propose the idea of completing image zoom using the bilinear interpolation algorithm on the FPGA,which is remain to be researched.