Research On Rapid Implementation Of Image Scene Matching Algorithm Based On DSP/FPGA

The high precision guidance weapons has been widely used in modern military affairs and using scene matching in guidance is a considerable means in improving the precision of the weapons. In scene matching guidance systems, speediness is an important issue. Based on the high speed digital signal processor TMS320C6711D combined with FPGA, we study how to improve the speediness of the system comprehensively.The thesis is mainly concerned with the follows:First, the composition and principle of the scene matching guidance system is introduced, and the structure and function of the real-time image processing module is described especially, then the principle of the image processing board based on TMS320C6711D is introduced.Second, four elements of the scene matching algorithm and variations of the image is studied. A scene matching algorithm based on gray feature coding is presented, the theory, approach and realization of the algorithm is given. And the result is analyzed, study of the algorithm on different conditions such as noisy, brightness and resolution is done, which proved better robustness and adaptability.Third, the issues about implement pretreatment algorithm in FPGA are discussed. Then the median filter is implemented in FPGA, the approach and flow is given, and the design approach of each key module is introduced. This implement get the best processing result with the least hardware resource. The control logic is easy, and the times span is arranged reasonable, which do not spend additional time of DSP, thus improve the system's speediness.Fourth, the SDRAM controller is implemented in FPGA, the composition and theory of SDRAM is introduced, which includes the initialization process, the control command etc. Through simplifying the state of the controller and costuming the working flow, the design of the controller turns to be easy and cost less resource, which make the SDRAM more efficient and the whole system's capability is improved.Fifth, the technique which can accelerate the algorithm speed when performing in computer is discussed. Then method of implementing the gray feature coding algorithm in hardware is studied. The algorithm is divided into two parts, the coding part is implemented in DSP and the NNPROD part is implemented in FPGA. The hardware realization flow of the NNPROD is introduced, and the design method of each module is presented. The utilization of IP core makes the whole design fast and efficient. Finally the feasibility of the design is proved, and system speed is accelerated.The overall study is reviewed and the future work is presented at the end of the thesis.