FPGA-based Image Denoising Processing And Hardware Implementation

Nowadays image transmission has been applied to all aspects of life,however noise is unavoidable in images.With the continuous development of computers,people have higher requirements for image processing.In the process of image transmission,there are various kinds of noises that affect the image quality.At present image denoising and real-time transmission are the key issues in the field of image processing and machine vision.Scholars at home and abroad have done a lot of research on image denoising,but the scheme of real-time image sharpening is not enough.How to process real-time images is a very important research direction.In order to solve this problem effectively,this paper designs a real-time image processing system based on the chip of FPGA.The main contents are as follows:(1)Taking salt and pepper noise as the target and 256*256 Lena classical gray image as the material,several classical denoising methods are studied theoretically.Analyzing the denoising principles of each algorithm and comparing the denoising effects of different filtering methods.The algorithm is simulated by MATLAB software.(2)According to the characteristics of salt and pepper noise,the simple and effective median filter is selected as the main means of image denoising.To overcome the limitations of traditional median filtering algorithm,it is not only required to be implemented faster in hardware,but also to be able to process the image more effectively to make the image clearer.(3)The image processing is designed and simulated by ISE tools produced by Xilinx Company and Verilog HDL hardware language.The flow chart of the hardware algorithm,part of the source code and the image simulation diagram are display.Finally,The performance of the implementation algorithm based on FPGA is analyzed.