Design And Implementation Of A Radiation-Hardened-by-Design Phase-locked Loop

PLLs have many applications in integrated circuits ranging from agile frequency synthesis and clock recovery circuits. Single event transients (SETs) will impact the PLL circuits causing phase and frequency shift and result in loss of PLL frequency lock which can have a catastrophic effect on the system. Therefor the Single-event transients (SETs) have become a growing concern in phase-locked loop (PLL) circuits. The combination of experimental testing and simulation has enabled the understanding of SET effects in PLL.This paper analyses the sensitivity of the individual componets in a pLL and a radiation sensitivity weak point has been identified as the charge pump (CP). Using an impulse function or a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. Analysis of single event transients on PLLs demonstrates that the settling time of voltage-controlled oscillators (VCOs) control voltage due to a single event strike is strongly dependent on peak control voltage deviation, SET pulse width and settling time constantζ_ωn. And the peak control voltage disturbance decreases with SET strength or filter resistance RP. Furthermore, analysis in the proposed PLL model is validated by simulation results of Matlab and Hspice, respectively.A Low-pass filter(LPF) topology is presented based on the analysis of SET to reduce the SET sensitivity of CP with the potential of significantly improving overall PLL resistance to SET effects. A method of PLL design employing a dynamic compensative circuit has been implemented and a CP hardened PLL is designed and fabricated in 180nm CMOS technology. Simulations has been performed, and annlysis of the measured control voltage deviation and max output phase displacement demonstrate a 75% improvement and the measured setting time demonstrate 60% improvement in the SET response. The design effectively eliminates the charge pump as the most susceptible element in the PLL. Annlysis of the measured jitter of clock demonstrate a fifty percent improvement in phase noise. Also this hardened design technique can be applied to other CPPLL topologies.