FPGA Implementation And Testing Of Data Processing In The Spaceborne SAR Data Former

The Data Former is an important sub-system in the receiving channel of SyntheticAperture Radar (SAR), which carrying on video signal processing under the control ofrada monitor. The maximum data rate of Synthetic Aperture Radar (SAR) system canachieve several millions bit per second (Mbps). The raw data must be compressed totransmit to the Ground. Data Compression was realized primarily through FPGA.Because the Data Former has the multi-sampling rate, multi-mode and high reliabilitycharacteristics, it brings the huge challenge for the FPGA design and the verification.Aiming at the characteristics of Data Former, this dissertation mainly studies the contentas follows:1. Taking the reference of the current advanced ASIC design methodology, usingthe current most advanced EDA tools, this dissertation summarizes a new developmentflow for high complex, high reliable FPGA, introduces every step in the design flow indetail, including corresponding concept and EDA tools. This dissertation mainly studiesthe advanced design and verification method of FPGA. It is valuable for the design andverification of FPGA in Data Former, especially for verification.2. In the FPGA of Data Former, there are many clocks domains. In these clockdomains, it's inevitably to pass control signal and data form one domain to otherdomains. It may lead to synchronization failure and metastability without careful designA design based on FPGA which implements adaptive synchronizer is presented, theproblem of synchronization failure in the Data Former with multi-sampling rate was solved.3. The performance of AD converter in Data Former directly affects theperformance of data-processing, therefore it needs to test ADC effective number of bits.This dissertation introduces the method and conditions of the testing. With a samplingdata of Data Former, get the test result; separate the harmonic form the noise, calculatethe effective number of bits (ENOB_SNR), based on the sine wave fit, analysis the sourceof the noise which deteriorate the effective number of bits of ADC. It is valuable forincreasing the effective number of bits of ADC and improving the system anti-noiseperformance.