VLSI Design Of H.264 CAVLC Decoder

H.264,the next-generation video coding standard,is jointly developed by the ITU and ISO/IEC.It has better compression efficiency than previous coding standards,and it is also network-friendly,which makes it suitable for many kinds of network.This thesis is just about the VLSI design of H.264 CAVLC decoder. While CAVLC(Context-adaptive Variable-length Coding) is an important entropy coding method in H.264,it is supported in baseline profile,main profile and extended profile.This thesis is based on H.264 baseline profile,aims at designing a CAVLC decoder fit for real-time video communication applications using VLSI design methods.Different from common VLC(variable-length coding),CAVLC can choose the best codeword table according to previously coded symbols,and thus brings about great compression efficiency for entropy coding.This thesis investigates the principles and procedures of CAVLC encoder and decoder,and gives specific examples.Based on the solid understanding of CAVLC decoding procedure,a VLSI design of CAVLC decoder is accomplished in this thesis.The design adopts a first-one detector to divide the complex codeword tables,and improves the speed of table lookup;in addition,a controller that manages all the decoding sub-modules is also proposed.This design is described using Verilog HDL,and it takes 62 clock cycles at most to decode a 4x4 block. The functional and gate-level simulation shows that it can correctly decode successive input bitstream.This design of CAVLC decoder is synthesized in Synopsys Design Compiler,using TSMC 0.18 um CMOS technology.The synthesis result shows that the maximum clock frequency is 41.67MHz,with an area of 8.9k gates and dynamic power of 3.28mW.This decoder can basically meet the real-time decoding requirement of 4CIF video.