Research On VLSI Design Of Entropy Encoding In H.264

With the development of video compression technology, computer, communications technology and microelectronics technology, H.264/AVC compression standard becomes a new birth for us. Compared with previous compression standards, H.264/AVC has higher compression ratio and network-friendly features, it can save more than 60% bit rate compared to MPEG-2 and save 40% bit rate compared to MPEG-4 in the same video quality. This is due to the using of key technologies, such as intra prediction, multiple reference frame motion compensation, and enhanced entropy coding. But its encoding complexity increased significantly, making the feasibility of applying real-time encoding can not be guaranteed, and huge computation will cause serious power consumption. Therefore, the study of H.264 VLSI is very important.Enhanced entropy coding is one of the H.264/AVC core modules, including context-based adaptive variable length coding (CAVLC), and context-based binary arithmetic coding (CABAC). CAVLC can choose different code-table adaptively by using of context information; CABAC do not need code-table, it updates the probability estimates and uses an adaptive binary arithmetic coding. So it more approaching the Shannon theorem, but the implementation complexity of CABAC is much higher than CAVLC.The research on CAVLC VLSI in this article includes that analysis the advantages and disadvantages of different architectures firstly and analysis CAVLC coding theory and algorithms because of its features of many code-tables secondly and optimization CAVLC coding structure and an efficient compromised structure between area and speed was given at last. The using of search method based on pretreatment improves the structure of look-up table (LUT). So it can quickly get the corresponding code word and code length; the using of arithmetic calculations instead of lookup table and the using of expansion share technique reduces critical path in the non-zero coefficient level coding module and the using of top bit of sum to realize modulo operation in the code word connection module.The research on CABAC VLSI in this article includes that analysis the coding theory and process, which includes binary processing, context modeling, and binary arithmetic coding (BAC). Binary processing is a pre-process of CABAC, it transfer non-binary synal element (SE) into correspondent binary strings (bins), and assign correspondent context model index to each binary string. Then each binary string and its context model index went into BAC, BAC output the coding results and updated the context model index. Because binary processing connects with others modules in system closely, so it was done by software. The CABAC core module, which is binary arithmetic coding, was designed and optimized by hardware. The traditional implementation has low throughput because of binary arithmetic coding's serial coding features, particularly the process of normalization and output section cost many clock cycles.Therefore, a four-staged pipeline architecture was proposed to improve the throughput in this article. The forwarding technology solved the data related hazard when updated the context of the model, and the using of carry save adder (CSA) to achieve a compromise between area and speed efficient and the fast architecture was designed for normalization process. The throughput of our proposed BAC can deal with a binary string (bin) per clock.Verilog HDL was used to achieve RTL level design for proposed architecture, and then simulation and synthesis was completed. Simulation results and performance analysis show that the proposed architecture is effective and can meet the requirements of entropy coding for the real-time high-definition 1920×1088-30fps video encoding.