The Design And Implementation Of SOC Debugging Technique Based On DW8051

On account of the semiconductor production improvement, SOC (System On Chip)are the focus of IC technology research, as the complexity of the chip functionalityincreases, in the process of developing SOC and designing chip, a novel debug schemecan help engineers detect and correct design bugs faster to shorten the product cycle.The traditional debugging method of SOC, which is dependent on the simulationsoftware and logical analysis instrument, impropriates too much system resources, alsoit has no capability of real time tracing and setting breaking points, so the debuggingefficiency is low. OCD (On Chip Debugging) have greatly changed the traditionaldebugging methods, improved the debugging efficiency, and the resulting known as a"JTAG"(Joint Test Action Group) debug Principle.The technology of JTAG was only applied for boundary scan testing at first,because of its high flexibility, it is used for supporting other functions gradually. Inorder to achieve the purpose of on chip debugging by JTAG technology, the JTAGinstructions are extended and the control logic used for supporting on chip debugging isadded in processor.At the beginning, this subject introduced SOC debugging technology and JTAGstandard, this subject has improved the structure of JTAG on the foundation of carefuland deep analysis of IEEE1149.1standard and accorded with the actual conditions,such as extending the JTAG instructions and adding Embeded ICE module to supporton chip debugging function. Then, logic circuit of supporting the debugging on chip isadded to DW8051after deep analysis which is the research object of this subject.Finally, the result of function test and performance analysis indicates that basicdebugging fanctions have been achieved in this OCD system.