Design And Implementation Of The High Performance M-DSP Emulation/Test Unit

Today,the leap-forward development of DSP brings booming room for digital information embedded in people's life, and vigorously promote the digital fusion of communication, computer and electronics products;the combination of DSP technology and the internet of things will play a key role in communication, e-commerce, multi-domain intelligent wearable devices, smart home and smart city construction. Undoubtedly, DSP technology shines in this fast-growing mobile Internet era.M-DSP is designed and developed by the School of Computer Science, National University of Defense Technology, with independent intellectual property rights of 32 high-performance floating-point vector dual-core processors. Main frequency reaches up to 1.1GHz, with very long instruction word(VLIW) structure,Dispatch unit can simultaneously parallel transmit eleven instructions by using variable length 16/32 bit RISC instruction set which is an efficie nt 14-stage pipeline structure.M-DSP is a high-performance floating-point vector processor which is facing on wireless communications, video and image processing, gearing to the needs of DSP market.With the rising improvement of DSP chip, its design is more complex and larger in terms of hardware scale. but the verification of DSP chips in the design process turns into an increasingly larger proportion. In the design process, inevitably there will be some BUG and error, which should attract high attention as it will affect the development of the entire chip. people pay increasingly attention to the chip emulation / debug functions, which also makes higher demands for designer. supporting simulation / debugging functionality without impacting the chip performance requires special consideration when designing.Therefore, this research focuses on the designing and implementation of M-DSP processor emulation / debug components. the main designing task and innovations are as follows:1. The paper designs and implements an in-chip emulation / debug components, which can effectively support JTAG-based debugging platform. tasks of emulation / debug are the precise control of pipeline, the access to each chip resource, and the statistics for system performance parameters.2. It designs and optimizes the logic of M-DSP processors dispatch unit, and manages to achieve the hardware support of the dispatch unit for ET software breakpoint for the 16/32 bit variable-length RISC instruction in M-DSP.3. It presents a simulation-based PCIE / debugging components program. through the logic reuse of the JTAG-based emulation / debug components, it achieves a DSP emulation / debug design for PCIE or ARM chip.4. Based on the characteristics of the on-chip emulation / debug components and Verilog PLI interface, it designs a verification system in the integration of M-DSP software and hardware through the joint of shared memory area of in integrated development environment(IDE), effectively achieving the full-chip simulation / debugging.5. by combining NC_Sim simulation with the integration of hardware and software based on the Verilog PLI technologies, it makes a comprehensive verification of the accuracy of the simulator / test unit.