Research And Implementation Of Timing Control Sub-system In Video Signal Process Chip

While digital TV becomes more and more widely used, lots of research institutes focus on researching and developing Video Signal Processing Chip which is the key component of recent digital TV. The Video Signal Processing Chip has the function of de-interlacing, scaling, frame raising up, image enhancement, etc.. It can convert lots of input video formats into others formats. The research subject of this paper is derived form"Tianjin municipal science and technology development's program– Video Signal Processing Chip research".This paper focuses on the research and design processing of the Timing Control Sub-system of this chip. As the key component of this chip, timing control sub-system can correspond and control the working flow of this chip, and it is divided into four function models: video format detecting module, center control module, display timing control module and test pattern automated generating module. The format detecting module can support PAL, NTSC and sixteen VESA formats. Reconfigurable display timing control module can support seventeen VESA formats. It can perform the function of clock compensation and clock locking to avoid video data underflow or overflow. The test pattern can generate eleven different patterns in order to inspect display panel and the algorithm of this video chip. Because of the widely used of display timing control module in SOC design, this paper also optimizes this module by adding APB interface in order to extending this module's using filed.In this paper, every module's design theory is discussed first, then top-down design method is used to divide every module into more material sub-structures. Each module's RTL code is designed according to division, and it is completely verified by SystemVerilog and verification methodology. At last, synthesis and P&R are also carried out by ISE. This sub-system's prototype is verified successfully by FPGA. Both coding and FPGA verification can prove that timing control sub-system can work well in this video chip.