Design And Realization Of System On Chips At Transaction Level Based On SystemC

The emergence of System on Chips (SoC) is considered as the revolution in microelectronics. When refers to that domain, from the prediction of Moore's law and the trend of evolution in design approaches, the integrate circuits will inevitably transfer to integrate systems at chip levels in 21st century. In the near future years, SoC will be composed of one or more chips and each chip may contain hundreds or thousands of processors which are regarded as the new logic gates. Along with the design complexity grows and time-to-market shrinks day by day, boost the abstraction levels of design becomes the mainstream of solution, and system level design (SLD) is the typical representation.An important branch of SLD at present is transaction level design (TLD) which employs SystemC as the very tool for implementation. But owing to the latter beginning of related researches to TLD and SystemC, there is a domestic lack of systematic guidance and basic theories in design processes. At the meantime, very few material cases could sustain the applications of study. In order to solve these problems, article addresses itself to the principle of TLD and realization of correlated models in detail.According to the theory of transaction level modeling (TLM) and by the approaches of software engineering, three sets of models of interconnection architectures on chip are designed and realized based on thorough analysis of advantages and traits of SystemC, and these models are simulated and validated at length by integrating some frames of references of mathematics and other tools of modeling. For one thing of this way is to reinforce and consummate the bases of TLD's theory, and give particular guidance to design approaches, for another is to establish integrated models of architectures to satisfy the requirements of SoC's exploitation in practical engineering. Totally speaking, outcomes and traits of this work are:①To improve the efficiency of design and speed of simulation, brings transaction level design of SoC based on SystemC in solving common problems;②To satisfy the practical engineering requirements of rapid contriving various SoCs, designs and establishes three integrated sets of models of interconnection architectures on chip at transaction level;③To supply fresh means and academically sustain, combines analysis and application of mathematic theories into transaction level design and validate; ④To deal with more complex design and validation, discusses how to make other tools of modeling compatible in design process which on the basis of SystemC.Transaction level models which are deployed according to results of this dissertation have been successfully applied into simulation and architecture explore of related embedded systems in war industry. The outcomes from the employment and function of models are favorable and steady.