Research And Implementation Of A Kind Of On-chip-bus Transaction Level Modeling

The IC(integrated circuit) technology have been great improved in the last ten years. The integration of IC has become extremely large scale, and a full electric system can be integrated in one chip, called SoC(system-on-chip). The development of IC has stepped into SoC times. The kernel technology of SoC design is based on IP Cores. There is much advantage of this technology. With the development of IP, The OCB(on-chip-bus) used to connect the IP Cores has become the main solution.The IC design method base on RTL has been widely used. With the increasing of design complexity and the demanding of design efficiency, Modeling, simulation, synthesis and validation on the level upon RTL, such as Transaction level, catch people's attention. Transaction level modeling (TLM) and simulating is much faster and efficienter than doing this at RTL. SystemC, with built in support for TLM, has accelerated the development of TLM methodology. The abstractive description ability of SystemC and the simulation speed promote the success of TLM.The basic theory and method of TLM are discussed in this paper. The property of SystemC, which fits for TLM, is presented. The TLMs(Transaction level Models) of Wishbone is completed based on the novel TLM theory with SystmeC, a powerful language. The WISHBONE System-on-Chip (SoC) Interconnection Architecture is a simple, flexible, open and free design methodology for use with semiconductor IP cores. The TLMs of two typical types of interconnection, point-to-point and shared bus, are finished with CoCentric System Studio. Some master and slave models with different behavior are created and are used to test the TLMs of Wishbone. The result shows that these TLMs of point-to-point and shared bus interconnection conform with the specification and can be used to connect master and slave device efficatively. It is also can be used to the system level design of SoC. The arbiter model with arbitration based on priority is accomplished, which can arbitrate different master and slave with unique priority. It is independent of the other parts of shared bus. So it can be reusable and easily replaced. The result also shows that simulation on transaction level is faster than on RTL.