DFT Design In Labeling Algorithm Chip

With the ever continuing improvement of the density and complexity of integrated circuits, the test of the Integrated Circuit is more and more difficult. Design for test has been the major method for the test of the chip. The coming of System-On-Chip (SOC) makes the test problem more severe, and put forward new requirement for the methodology and IC's design flow.This paper introduces various test method, fault mechanism, fault model and some standard IC test. Then some popular technology is summarized such as scan chain insertion, Built-In-Self-Test (BIST) and boundary scan method.The following content is to research the realization of DFT in the labeling algorithm chip based on analysis some DFT technology's characteristic. This paper introduces the architecture and labeling algorithm of the chip, and introduces the internal scan design, JTAG design and MBIST design. This paper introduces the structure design and instruction configuration of the boundary design. We use the tools of the Synopsys Corp accomplish the DFT design. Furthermore, Automatic Test Pattern Generation (ATPG) is used to verify the validity of DFT method. There are more than 1900 patterns and the test coverage is 95.69%, test time which is about 1200 period is well controlled.The MBIST of the chip use the Verilog design. This paper introduces various BIST algorithm and select the march13n algorithm, which can cover most of the faults. The waveform of the MBIST shows that design reach the request of the labeling algorithm. The result shows that this method can meet the test requirement.