The IP Soft Core Design And Verification Of Integer Discrete Cosine Transform

With the advancement of the technic of network and multimedia, the information technology has rapidly development recent years. The transmition of high-qualified multimedia information which people looking forward is limited by the bandwidth of transfer line. And the storage of information is limited by the capacity of memory. There is a demand for developing a new video compression standard, Such as AVS, because of Intellectual Property.Aiming to Intellectual Property design of Integer Discrete Cosine Transform based on AVS, the research on two issues is carried out in this thesis. One topic is focused on the study of Integer Discrete Cosine Transform and its IP core design. Another is focused on the implementation of Integer Discrete Cosine Transform(IDCT).Firstly, the fast algorithm based on IDCT is analysed and the result has shown that DCT-like matrix is suitable for hardware design compared to other similar works. Furthermore 8×8 transform matrix has better video compression performance than 4×4 transform matrix, and has its own Intellectual Property. Therefore the study of the thesis is focused on the characteristic of 8×8 transform matrix. Then, this thesis analyzes the hardwire structure of 2-D ICT based on row and column separated. Secondly, the Verilog HDL source code is developed, and the functional simulation is completed. The result of simulation confirms the design. Lastly, according to the design requirement of IP soft core, this 1-D ICT IP core is implemented core on VirtexII FPGA of Xilinx, and due to the powerful function of ISE 8.1, the performance is upgraded by using time approaching, which confirms this IP core. This paper gives more experiences and firm foundation to future research.In the final, the conclusion about the thesis and the future work are given.