2-D DCT/IDCT IP Core Design And Implement Using FPGA Technology

Discrete Cosine Transform(DCT) and Inverse Discrete Cosine Transform(IDCT) are most widely used image compression techniques and current standards for the compression of still(JPEG) and moving(MPEG-1,2,4 H.26x) images use DCT to remove spatial redundancy in images. It is difficult to make a real-time implementation of it by software method because it takes too many CPU cycles. Therefor we are trend to use hareware implementation to satisfy our requirement. This article is dedicate to the hareware implementation of 2-D DCT/IDCT FPGA core.This article first introduced the theory and advantages of using Discrete Cosine Transform and Inverse Discrete Cosine Transform in images compression. We portrayed the process of using DCT/IDCT in image compression, compared it with several other transforms such as DST, DFT. Then we made a vivid discussion among several fast DCT algorithms and made a conclusion of such algorithms.In this article we proposed two different resolutions to fast DCT transform. Both of them enroled the pipelinning technology and use the Row Column decomposition Method (RCM) to decompose the two demensional DCT into one demensional DCTs. When calculating the 1-D DCT/IDCT, we made some improves in Loeffler's fast DCT algorithm according to the characteristics of image compression. After rearrange and simplifying the calculation cycles, we got a shorter critical path and thus speed up the pipelling. We programed the IP core and synthesized it under the MERCURY series FPGA chipset, and at last we proved it by cycle accurate simulation.The synthesize result shows one of our DCT/IDCT IP core can run as fast as 116 MHz, it takes 2827 Logic Elements(LEs). the other one can run as fast as 74 MHz, but it just takes 1629 Logic Elements.This work is sponsored by the National Natural Science Foundation of China. Proj. NO. 60173042.