Design Of JPEG Compress Coding IP Core Based On FPGA

The great technological progress with microelectronic technology and related industries promoted the rapid development of the paperless office automation. The application, transmission and storage of massive electronic information data, especially the image data, require the equipment to get faster data-processing speed and higher efficiency which brings great application and need of the image compression chip. As the technical core of SOC design, IP core reuse technology shorten the cycle of design with less failure risk and greatly promoted the development of the chip design. With the improvement of the process, cost reduction and performance improvement, FPGA develop the new from the old constantly. For its advantages of short design cycle, low cost and easy to modify and expand, FPGA gradually plays a more and more important role in dealing with complex digital signal processing system.This design, aiming to realize the image data compression IP core, comes from the TS series intelligent high-speed scanner project which refers to the FPGA data processing chip. This IP core can not only be applied in high-speed scanner, but also be suitable for other high-speed static image compression processing equipmentAccording to the top-down design principle the thesis gives a description of system module partition and RTL coding of each module in accordance with the content of the basic system of JPEG, based on the successful experiences of the existing JPEG compress chips. The realization is divided into three function modules including two dimensional discrete cosine transform (2-D DCT), quantification and zigzag scanning and Huffman coding. As the core of a JPEG compressor, the 2-D DCT module adopts the IP core reuse technology. The 2-D DCT is divided into two one-dimensional discrete cosine transform (1-D DCT) calculations based on the finite state machine control. The 1-D DCT implementation is base on the improved signal flow-graph algorithm with pipeline and parallel technology, improving its running speed. The study of this thesis is based on the FPGA chip Cyclone II series produced by the company of Altera. The RTL code design is written in VHDL. The thesis gives the synthesis and simulation results of IP core and its modules as well. The IP core reaches an operating frequency of 127 MHz.