The Design And Implementation Of A Decoder For Digital Television

With the development of data compressing technology and Internet, broadcast television digitization has got the development at full speed. How to receive and replay broadcast television programs on personal computers has become a promising research topic.This thesis concentrates on the design and implementation of a low-cost system receiving and decoding digital video with different standards. Also, it provides the implementation and optimization of IDCT algorithm. The system is developed on a Programmable Chip (SOC) with BDA framework, which software platform is DirectShow. The key design for digital television system is decoder, which leads to a new hierarchical reconfigurable architecture based FPGA. The decoder consists of a few arithmetic units like ALU and storage, and takes the task of decoding the video stream of different standards by reconfigure.In decoder, the video stream is divided into motion vector and coefficient data by VLD. The coefficient data is processed by zig-zag scan, Inverse Quantizer, and Inverse Transform. The motion vector is converted by Motion Compensation. Also, it provides the detailed analysis and optimization of a recursive decompose algorithm with higher efficiency and regular structure, which is specially applied in the computing of IDCT.The design of a video decoder is implemented, and quantitative analysis to the performance of the system is made. The testing result on the ARM ADS platform shows that the basic function of the decoding system has been performed, it can improve the performance of the system.