H.264 Decoder Chip To Achieve Its Multi-mode Extended, High-definition Television System

With the rapid development of digital technology, video equipment market has entered the turnaround from analog to digital. This gave rise to the huge market demand and a hundred-billion yuan market value. High Definition Television has been a research hot spot in recent years, which is directly related to the development trend of the domestic TV market. However, the vast majority of video decoder chip, which is the core device of High Definition Television system, still relies on foreign imports.With its high compression efficiency and network adaptability, H.264/AVC standard has become the mainstream of the digital TV standard. It has wide range of application areas and extremely broad market prospects. H.264/AVC video codec standard is in-depth studied in this thesis, and H.264/AVC decoder SoC chip is proposed. The chip can support H.264/AVC Main Profile 720p format.The system design for H.264/AVC decoder is discussed comprehensively in this thesis. This thesis also covers the functional prototype hardware verification and multimode multiplexing structure. Following aspects are discussed in this thesis: H.264/AVC video codec standard is in-depth studied, and its structure, process and algorithm are analysed too; Design strategy for H.264/AVC decoder based on SoC system is presented, and the implementations for the key modules are deeply discussed; The principle of software/hardware co-verification and the multimedia verification platform based on the ADSP-BF537 are presented detailedly, and H.264 decoder is verified based on these; The multimode codec multiplexing structure is presented, and the implementation for mltimode expansion of H.264 decoder is discussed too.H.264 decoder SoC chip is implemented by Verilog HDL, and the decoder IP core is validated on FPGA verification board. And then, the 53MHz working frequency can be achieved.