The Hardware Design And Realization Of MPEG-2 Video Decoding System

In recent years, the step of conversion from analog TV to digital TV has become obviously faster and faster, indicating a new digital TV era. As a result, digital TV technology-related research has been paid more and more attention. Digital TV signals use MPEG-2 codec standards and therefore MPEG-2 decoder design has become a popular research.This paper mainly research on MPEG-2 standard method and the design and realization of the whole circuit of the video decoder. In the paper, the structure design of MPEG-2 video decoder system is optimized, studing the various sub-module structure and method. On the basis of design and validate a number of related sub-circuit module to improve the new method. The present research papers on MPEG-2 video decoder system of work are as follows:1. Through the study of MPEG-2 video decoder system structure and characteristics of the principle, designing an optimized structure of the decoder. It supports MPEG-2 standard in the MP @ ML streams, which uses Verilog hardware description language for describing and verification.2. Designed emultiplexing modules to extract any set of programs in the video stream and analysis of the video stream of video information analysis module, including a new variable-length code decoding circuit.3. Designed an inverse scan and inverse quantization circuit suitable for MPEG-2 decoder, and put forward and realize a IDCT optimized the structure of the new circuit.4. Designed a motion compensation for MPEG-2 module. In the module designed pixel cache modules, simplify the unit's forecasts predict a half-pixel basis, to improve the efficiency of the forecast.