CORDIC Based Reconfigurable Processing Unit Architecture Research And Design

Driven by the new generation applications such as 3G mobile communication, digital video/audio, etc, the requirements on speed, performance, cost and flexibility are swelling rapidly. All these requirements conflict to each other in the architecture domained by DSP executing software and hardwared ASIC. The general software processing method of DSP has very strong adaptability, but degrades the performance. On the other hand, ASIC could reaches high performance, but has high cost and narrow application range. The contradiction between generality and computing performance becomes sharp. It is urgent to a revolutionary computing technology. Reconfigurable computing is very accordance with above requirements.Reconfigurable computing combines the advantages of DSP and ASIC, which has not only high performance and high reliability of ASIC, but also high flexibility and programmable function of DSP. Reconfigurable computing could give consideration to multiple requirements, which will become a mainstream computing mode.Based on the research of reconfigurable computing technology and DSP, some computational structure and function of typical DSP algorithms are analyzed further in the thesis in order to summarize the hardware structure characters for different algorithms. DSP algorithms based on convolution are suitable for implementation by DSP with MAC structure. DSP algorithms based on rotation structure can be implemented by CORDIC method. Common parts are summarized and a unified reconfigurable computing modular has been designed. With the reconfigurable interconnection, a pipelined CORDIC based reconfigurable processing unit has been completed. Finally, different algorithms have been mapped into the same structure.