The Routing Structures Design Of Computing Array In Reconfigurable Processor For Radar Applications

The reconfigurable processor is a new ideal solution to deal with the radar signal processing which combine the flexible calculation of software and the high efficient calculation of hardware in one. The reconfigurable array is the calculation core in the reconfigurable processor. The structure of the route is the organizer in the reconfigurable array. The performance of the calculation in the system depends on its efficiency and flexibility. The reconfigurable route is the interconnection to provide data exchange channel between the reconfigurable units and the bypass calculation unit as well as the distributed register to expand the range of the actual application of reconfigurable array and increase the pipeline efficiency. However, the interconnection is the main architecture of the route, the bypass calculation unit and the distributed register are extended function to calculate the array and storage s pace. Hence, in this thesis the structure of the route is mainly focused on the design of the interconnection, the others are separated in the design of the array and the register.The implementation method using reconfigurable parallel process and the basic structure of the reconfigurable system are discussed in this thesis. The data flow function of the core operator is analyzed as a significant part. At the beginning, using the data flow function of the core operator as the basic theory derived the reconfigurable operator RASP prototype facing the radar application. Then the design of the calculation array and register which are related to the structure of the route and the design of the interconnection method are analyzed. First, according to the diverse calculation processes of the core operator, the heterogeneous array of multi-domain collaborative design is proposed, making the reconfigurable array support calculation of various categories of pipeline processing. Secondly, in order to solve the problem of limiting the performance of the pipeline, which is because of the large amount complex data transporting to the array, the different dual port data transported design is proposed in this thesis. The data transport process is simplified and this completely meets the needs of pipeline data processing. Thirdly, to solve the problem of the source waste and bad calculation performance in the organization of the core operator pipeline of the traditional interconnection, the structure of the multi-mode interconnection of the reconfigurable processor array is proposed. It can not only meet the requirement of data process with complex process and diverse algorithm, but also realize the efficient parallel array calculation. Last but not least, the core processor process is divided into some steps based on the calculation flow. Additionally, the calculation in each step is split into some basic calculation structures which are matched to the size of the array, then cyclic mapping array to complete the calculation.The experimental results show that the proposed multi-mode interconnect structure can highly improve the calculating performance. When referring to the 64K-point FFT, the 1K-point 128-Tap FIR, the 96-order matrix inversion, the performance improves 2.38 to 3.4 times than mainstream interconnect structure. In addition, the using rate of the Process Elements in the Reconfigurable Computing Arrays is promoted by 1.13 to 2.38 times. Compared to the mainstream Reconfigurable Processing Architecture, the proposed RASP architecture performs better in not only computing performance, but also the flexibility of computing, which satisfy the requirement of high performance and high flexibility in Radar Signal Process Applications.