Research And Design On Reconfigurable Coprocessor Architecture For Image-processing Application

The image manipulation nowadays desiderates the super high performance for the data processing to satisfy the real-time requirements, which traditional processor architectures are unable to meet. So it's necessary for us to research on how to realize the image manipulation. Reconfiguable computing system combines the flexibility and high-performance, which makes it a new solution for the application.The thesis proposes IRC, an Image Reconfiguable Coprocessor model, targeted at image processing applications. Based on the IRC model, we explored the architecture design of the reconfigurable processing unit. The research work of this thesis mainly includes: Research on the reconfigurable computing and its system architecture, proposes IRC model, which consists of reconfigurable processing unit, PU array architecture, IRC controller, context memory and data buffer; Analyze the design targets of IRC context words according to the characteristics of image applications, and presents the IRC context system; Design and implement the architecture of Reconfigurable Processing Unit, which consists of MAC and ALU; Research on the mapping some important image compression algorithms on the IRC model, like DCT, and evaluate the performance of IRC model, which shows the performance of IRC is higher than any other system.At last, the further study on IRC is discussed, which releases the the research to be done in the future.