Research Of Retime Solution For H.264 Encoder On Dual Core DSP

Compare with all previous video encoding standards, H.264 has higher encoding efficiency. However, the higher encoding efficiency is based on the increase of computational complexity. The higher complexity has affected the industrialization process of H.264 to some extent. Many companies and research institutions try their best to explore the real-time solution of H.264 Encoder in embedded system, especially in DSP (Digital Signal Processor) platform. However, as the high complexity and the resources limitation of the embedded system, there has no good solution up to now.In allusion to the system architecture of ADSP-BF561 of ADI (Analog Devices Incorporation) and the characteristics of the H.264 encoding algorithm, transform, quantization, de-quantization, inverse transform, entropy coding and loop filter, border expansion, half Pixel interpolation were assigned to both of the Cores of ADSP-BF561, respectively, and Cache and DMA (Direct Memory Access) were choosing as the data scheduling strategy. Meanwhile, code optimization has eased the DSP resource constraints to some extent. Finally, a complexity reduction algorithm for motion estimation is proposed. The proposed algorithm can achieve computational savings of 8.33%–33.33% (depending on the source video sequence) with no significant loss of rate-distortion performance.Simulation results demonstrate that the optimized H.264 Encoder achieve higher encoding frame rate (up to 30 fps) for the video sequece of CIF (352×288) format with no significant loss of rate-distortion performance. However, it need for further study and optimization for the video sequece of VGA (640×480) format.