Signal Integrity Simulation Method Of DDR SDRAM System Based On IBIS Model

Today's computer and semi-conductor technology are developing rapidly.The read/write speed and capacity requirements of memory chips have also increased.DDR SDRAM is the main form of contemporary memory chips,and its transmission rate has reached 3,200 MT/s.Designers must face a series of signal integrity such as reflection,ringing,crosstalk,and insufficient timing when designing printed circuit boards for memory systems.Signal integrity is a big concern of DDR SDRAM system design.Adding signal integrity simulation process to early design stage is one of the most effective solutions to avoid high-speed signal integrity problems.This paper researches signal integrity issues of DDR SDRAM memory system.The specific implementation is an example of one field programmable array chip drives nine DDR4 memory chips.The main work includes IBIS model verification and simulation,schematic design and topology optimization,simulation,design rule optimization,printed circuit board layout and comparison of simulation with test results.The simulation results well match the actual test results.It is proved that the method of signal integrity simulation of DDR SDRAM system based on IBIS model can predict the performance of the whole system channel.The issues of high bit error rate of DDR SDRAM system can be solved in advanced.It helps improving signal performance of DDR SDRAM system products and reducing the development cycle.