| Video Signal Process Chip is one of digital TV core chips. This chip's main function is to converse the source digital signal of TV to the format of the target display. In addition, it has some assistance function such as image boost up, OSD and so on. As the development of digital TV, this chip shows huge development potential and market foreground.Spatial resolution transformation system, which is composed of frame rate up-conversion subsystem, de-interlacing subsystem and scaling subsystem, is part of Video Signal Process Chip. The thesis focuses on the design and implement of spatial resolution transformation subsystems, including frame rate up-conversion subsystem and video scaling subsystem.For the frame rate up-conversion subsystem, based on the analysis and study of many motion estimation algorithms, this thesis proposes a new block-based motion-compensated frame interpolation algorithm, which keeps good performance while using fewer hardware resource. Motion estimation unit of the new algorithm is implemented in the paper.For the video scaling subsystem, this paper researches and discusses the scaling- down and scaling-up algorithm respectively, considering the need for implementing PIP(Picture in Picture) function. Scaling-down algorithm is to generate sub-picture, and scaling-up algorithm for main-picture. After studying many algorithms, the paper puts forwards a scaling-down algorithm based on image sub-block, which has good performance, but simple and easy to implement.For the scaling up, bicubic algorithm is adopted. By configurable design, 3 kinds of wide screen display modes and switch among them is implemented. In addition, this thesis proposes a hardware structure for chip with the function of PIP, and analyzes and discusses its feasibility.Finally, this paper conducts the function simulation and verification for the spatial resolution transformation subsystems, and gives the simulation results and FPGA realization pictures. |
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