Research And Design Of Image Processing Subsystem In Multi-Standard Video Post Processing Chip

Video Signal Process Chip is one of the key chips of digital multimedia, which is mainly used in conversing the source video signal to the format of the different display equipment. The chip's main function includes frame frequency conversion, de-interlacing, image scaling, image enhancement, OSD and so on.For the special function target, this dissertation research and design a video image process subsystem, which include image scaling, image enhancement and output time sequence control, and it can support many VESA formats. This dissertation focus on the research and circuit design of image scaling and image enhancement.In the structure design of the vedio image process subsystem, this dissertation use only some line buffer which is single port RAM instead of frame buffer, which can reduce the area of chip. This subsystem has no function of global control, so every part woks in the highest efficiency which make the systems efficiency higher.By analyzing and comparing some linear interpolation arithmetic, bicubic interpolation is choiced to be the basic interpolation arithmetic. In order to improve incompatibility between images and display format on their wide-high scale, this thesis researches a non-linear interpolation arithmetic, which apply the resolution conversion from common screen to wide screen. This arithmetic can make the visual effect better than the common linear scaling in processing different wide-high scaling. The scaling circuit can support much VESA standard, and the highest resolution is 1920x1200,the lowest resolution is 640x400. There are 3 kinds of display modes, linear scaling, non-linear scaling and letter-box. The display mode is configurable, so audience can switch among them.This thesis designs skin color process arithmetic to search skin area of image and change the color, which can make a favorable visual effect. The direction and magnitude of changing can be switched by configurable design.Finall, this theis conducts the function simulation and verification for the video image process subsystem. The time sequence and result image has achieved the design target.