Investigation On Video Format Conversion Technology And Its VLSI Design

As one of the most important chips in DTV and DPTV, video format conversion chip has a huge commercial value. Its main function is converting different input video formats into a given one through digital signal processing flow. It comprises de-interlacing, frame rate up-conversion, scaling and many image enhancement processes.Due to the diversity of input video formats, the complexity of processing algorithms and viewers'high requirements on image effect, it is necessary to overcome two difficulties to implement the chip: one is developing excellent video format conversion algorithms, which perfectly balance image effect and hardware expense; the other is designing high performance VLSI solutions.After investigating existing technologies, the author starts with developing video format conversion algorithms, expatiates on the VLSI implementation of key-algorithm blocks and the top-level system design of the chip, then analyzes the simulation results. Main contributions of the dissertation are shown below.First, sum up existing video format conversion algorithms; bring forward a motion-adaptive de-interlacing algorithm.Second, due to the operation characteristics of the de-interlacing algorithm, a motion-value stored data transfer strategy and zigzag FIFO structure are proposed to reduce hardware expense and alleviate computational burden.Third, to deal with difficulties in designing the chip, the author brings forward two top-level control strategies and related top-level system solutions for the chip, compares them in several aspects, such as robustness, extensibility and real-time processing ability, then draws a conclusion.