Digital Baseband Design Of RFID Tag Chip Using RRAM

As one of the key technologies of the Internet of Things sensing layer,Radio Frequency Identification(RFID)technology has received increasing attention.However,the development and application of traditional RFID technology are gradually facing bottlenecks.For example,it is still difficult to achieve uniformity in the international standards for RFID technology;Because of the problems in performance,power consumption and process compatibility,the Electronic Erasable Programmable Read Only Memory(EEPROM)used in traditional RFID tags has been unable to adapt to higher requirements and newer processes;Due to the lack of new technology solutions,the cost of RFID tags is always high.In order to solve the above problems,this paper studies the design and implementation of digital baseband circuit of RFID tag chip based on Resistive Random Access Memory(RRAM),combining the advantages of new type of RRAM in reading and writing speed,reading and writing power consumption,cell area and CMOS process compatibility.The main contents of this paper are as follows:In this paper,the 1~3 part of ISO / IEC 14443 near-field communication protocol is taken as the design standard of RFID tag chip,and the design of RFID tag digital baseband and and corresponding test platform is completed.First of all,this paper analyzes the signal interface,initialization and anti-collision,state jump and other contents of ISO/IEC 14443 protocol,and formulates the instruction set,design function,interface standard and other requirements of the chip.Secondly,this paper analyzes the overall architecture of the chip,and introduces the structure and function of the main modules such as RF front-end circuit,RRAM and its peripheral circuit.And then,as the focus of this paper,according to the top-down design idea,the digital baseband part of the chip is divided into several sub modules such as improved Miller decoder,verification module,main control module,response processing module,RRAM control module,encryption / decryption module,Manchester encoder and test interface module,and the interface standard between them is determined.Next,Verilog HDL is used to complete the design of sub module and top module respectively.In the subsequent work,this paper used Design Compile tools to physically synthesize digital basebands and generate gate-level netlists,and then used IC Compile to physically implement the design.In the end,the design has been verified by physical verification,Static Timing Analysis(STA),and Dynamic Timing Simulation(DTA).The results show that the digital baseband circuit of the RFID tag designed in this paper can correctly fulfill the expected functions specified in the instruction set,and meet the ISO / IEC 14443 agreement and the final sign-off standard.