Design Of 400MHz～950MHz PLL For Communication And Math Modeling

This paper is focused on the design of frequency synthesizer used for communication system such as interphone, cordless phone whose output frequency range is around 400MHz~950MHz, phase noise is less than -80dBc/Hz@10KHz and the total harmonics distortion is less than 3%.After completing pre-simulation and layout realization, the circuit has been taped out in TSMC.35um and tested using spectrum analyzer.The design method of Top to Down is used. Firstly, the whole structure of PLL is introduced. Then each module is separately described, different topology is balanced and the ones used in this design are presented. Secondly, design of VCO is emphasized, and based on introduction of VCO and PLL system basic phase noise theories, some practical phase noise decreasing technologies are proposed. Finally, layout and verification of PLL circuit is completed and the PLL has been taped out.The key point is the design of voltage controlled oscillator. Due to the package effects, two unperfected states exist in VCO: one is the dual-loop oscillation mode owing to bonding wire inductor, the other is that oscillation condition is affected by metal resistor. For solving this problem, a math model of completed loop has been set up, and the boundary point can be found easily, then the result is consistent with Spectre simulation.A method of solving circuit problems in virtue of math model has been proposed, then the design efficiency and product yield could be improved. The achievement of this paper will provide good guides and practical references on the design of PLL.