Current Mode Pipelined CMOS A/D Converter

Recently, with the rapid development of wireless communication, analog–to-digital, one of key techniques, is being made amazing progress due to the more and more demand from products. Pipelined ADCs, one of the most popular ADCs, are mainly used in those fields which look after both resolution and speed, such as wireless LAN in communication, cell phone and high-resolution digital TV in custom electronic products.On the other hand, with the explosive growth of deep sub-micrometer and portable devices, the supply voltage of integrated circuits becomes lower and lower, even lower than 1V. As one important part of system, the analog-to-digital (ADC) also needs to adhere to the low voltage and the low power constraint, hence longer battery lifetime.In present dissertation, current-mode signal processing technique has been adopted to design a 10bit pipelined ADC in order to lower power. Main work of this dissertation includes:①By analyzing a great deal of pipelined ADC, the structure of nine 1.5bit-resolution stages is adopted. Each stage contains current sample/hold(CSH),current mirror(CM),current comparator and current steering DAC (digital-to-analog converter).②The application of second generation current convey (CCII) to current ADC is proposed. A CCII-based current mode pipelined ADC is designed. The proposed ADC can achieve 10bit resolution with 1V power supply at the 50MHz sampling rate. The ADC is simulated with the HSPICE software. Simulation results show the feasibility of the proposed ADC.③A CCII-based current S/H circuit is designed by using zero-voltage sampling technique to improve the accuracy of sampling current. The circuit is simulated with the HSPICE software. Simulation results show that the proposed circuit has good performance.Lastly a conclusion and prospect of this paper have been done.